 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| freescale semiconductor data sheet: technical data contents ? freescale semiconductor, inc., 2008,2012. all rights reserved. document number: MPC5565 rev. 3, may 2012 this document provides electrical specifications, pin assignments, and package diagrams for the MPC5565 microcontroller device. for functional characteristics, refer to the MPC5565 microcontroller reference manual . 1 overview the MPC5565 microcontroller (mcu) is a member of the mpc5500 family of micr ocontrollers built on the power architecture ? embedded technology. this family of parts has many new features coupled with high performance cmos technology to provide substantial reduction of cost per feature and significant performance improvement over the mpc500 family. the host processor core of th is device complies with the power architecture embedded category that is 100% user-mode compatible (including floating point library) with the original powerpc instruction set.the embedded architecture enhancements improve the performance in embedded applicati ons. the core also has additional instructions, including digi tal signal processing (dsp) instructions, beyond the original powerpc instruction set. 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . 5 3.3 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 emi (electromagnetic interference) characteristics 8 3.5 esd (electromagnetic stat ic discharge) characteris- tics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 voltage regulator controller (vrc) and power-on reset (por) electrical specifications . . 9 3.7 power-up/down sequencing . . . . . . . . . . . . . . . . 10 3.8 dc electrical specifications. . . . . . . . . . . . . . . . . . 14 3.9 oscillator and fmpll electr ical characteristics . . 20 3.10 eqadc electrical characteristics . . . . . . . . . . . . . 22 3.11 h7fa flash memory electr ical characteristics . . . 23 3.12 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.13 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4 mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.1 MPC5565 324 pbga pinouts . . . . . . . . . . . . . . . . 46 4.2 MPC5565 324-pin package dimensions . . . . . . . 47 5 revision history for the MPC5565 data sheet . . . . . . . 49 5.1 changes between revision 2.0 and revision 3.0 . 49 5.2 changes between revision 1.0 and revision 2.0 . 49 5.3 changes between revision 0.0 and revision 1.0 . 52 MPC5565 microcontroller data sheet by: automotive and industrial solutions group
MPC5565 microcontroller data sheet, rev. 3 overview freescale semiconductor 2 the mpc5500 family of parts contains many new features coupled with high performance cmos technology to provide significant perf ormance improvement over the mpc565. the host processor core of the mp c5565 also includes an instruction set enhancement allowing variable length encoding (vle). this allows optional encoding of mixed 16- and 32-bit instructions. with this enhancement, it is possible to significa ntly reduce the code size footprint. the MPC5565 has two levels of memory hierarchy. the fastest accesses are to the 8-kilobytes (kb) unified cache. the next level in the hierarchy contains the 80-kb on-chip internal sram and two-megabytes (mb) internal flash memory. the internal sram and fl ash memory hold instructions and data. the external bus interface is designed to support most of the st andard memories used with the mpc5 xx family. the complex input/output timer func tions of the MPC5565 are performed by an enhanced time processor unit (etpu) engine. the etpu engine controls 32 hardware channels. the etpu has been enhanced over the tpu by providing: 24-bit timers, double-action hardware channels, vari able number of parameters per channel, angle clock hardware, a nd additional control and arithmet ic instructions. the etpu is programmed using a high-le vel programming language. the less complex timer functions of the MPC5565 ar e performed by the enhanc ed modular input/output system (emios). the emios? 24 hardware ch annels are capable of single-action, double-action, pulse-width modulation (pwm), a nd modulus-counter operations. moto r control capabilities include edge-aligned and center-aligned pwm. off-chip communication is performed by a suite of se rial protocols including controller area networks (flexcans), enhanced deserial/seria l peripheral interfaces (d spis), and enhanced serial communications interfaces (escis). the dspis suppor t pin reduction through hardware seri alization and deserialization of timer channels and general-purpos e input/output (gpios) signals. the mcu has an on-chip enhanced queued dual an alog-to-digital converter (eqadc).the 324 package has 40-channels. the system integration unit (siu) performs several chip-wide configuration f unctions. pad configuration and general-purpose input and output (g pio) are controlled from the si u. external interrupts and reset control are also determined by th e siu. the internal multiplexer submodule provides multiplexing of eqadc trigger sources, daisy chaining the dspi s, and external interrupt signal multiplexing. ordering information MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 3 2 ordering information figure 1. mpc5500 family part number example unless noted in this data sheet, all specifications apply from t l to t h . table 1. orderable part numbers freescale part number 1 1 all devices are ppc5565, rather than MPC5565 or spc5565, until produ ct qualifications are complete. not all configurations are available in the ppc parts. package description speed (mhz) operating temperature 2 2 the lowest ambient operating temperature is referenced by t l ; the highest ambient operating temperature is referenced by t h . nominal max. 3 (f max ) 3 speed is the nominal maximum frequency. max. speed is t he maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm; and 135 mhz parts allow for 132 mhz system clock + 2% fm. min. (t l )max. (t h ) MPC5565mvz132 MPC5565 324 package lead-free (pbfree) 132 135 ?40 c 125 c MPC5565mvz112 112 114 MPC5565mvz80 80 82 MPC5565mzq132 MPC5565 324 package leaded (snpb) 132 135 ?40 c 125 c MPC5565mzq112 112 114 MPC5565mzq80 80 82 mpc m 80 r qualification status core code device number temperature range package identifier operating frequency (mhz) tape and reel status temperature range m = ?40 c to 125 c package identifier zq = 324pbga snpb vz = 324pbga pb-free operating frequency 80 = 80 mhz 112 = 112 mhz 132 = 132 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre qualification m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow 5565 zq note: not all options are available on all devices. refer to ta b l e 1 . MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 4 3 electrical characteristics this section contains detailed information on power c onsiderations, dc/ac electric al characteristics, and ac timing specifications for the mcu. 3.1 maximum ratings table 2. absolute maximum ratings 1 spec characteristic symbol min. max. unit 1 1.5 v core supply voltage 2 v dd ?0.3 1.7 v 2 flash program/erase voltage v pp ?0.3 6.5 v 4 flash read voltage v flash ?0.3 4.6 v 5 sram standby voltage v stby ?0.3 1.7 v 6 clock synthesizer voltage v ddsyn ?0.3 4.6 v 7 3.3 v i/o buffer voltage v dd33 ?0.3 4.6 v 8 voltage regulator control input voltage v rc33 ?0.3 4.6 v 9 analog supply voltage (reference to v ssa )v dda ?0.3 5.5 v 10 i/o supply voltage (fast i/o pads) 3 v dde ?0.3 4.6 v 11 i/o supply voltage (slow and medium i/o pads) 3 v ddeh ?0.3 6.5 v 12 dc input voltage 4 v ddeh powered i/o pads v dde powered i/o pads v in ?1.0 5 ?1.0 5 6.5 6 4.6 7 v 13 analog reference high voltage (reference to v rl )v rh ?0.3 5.5 v 14 v ss to v ssa differential voltage v ss ? v ssa ?0.1 0.1 v 15 v dd to v dda differential voltage v dd ? v dda ?v dda v dd v 16 v ref differential voltage v rh ? v rl ?0.3 5.5 v 17 v rh to v dda differential voltage v rh ? v dda ?5.5 5.5 v 18 v rl to v ssa differential voltage v rl ? v ssa ?0.3 0.3 v 19 v ddeh to v dda differential voltage v ddeh ? v dda ?v dda v ddeh v 20 v ddf to v dd differential voltage v ddf ? v dd ?0.3 0.3 v 21 v rc33 to v ddsyn differential voltage spec has been moved to ta bl e 9 dc electrical specifications, spec 43a. 22 v sssyn to v ss differential voltage v sssyn ? v ss ?0.1 0.1 v 23 v rcvss to v ss differential voltage v rcvss ? v ss ?0.1 0.1 v 24 maximum dc digital input current 8 (per pin, applies to all digital pins) 4 i maxd ?2 2 ma 25 maximum dc analog input current 9 (per pin, applies to all analog pins) i maxa ?3 3 ma 26 maximum operating temperature range 10 die junction temperature t j t l 150.0 o c 27 storage temperature range t stg ?55.0 150.0 o c electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 5 3.2 thermal characteristics the shaded rows in the following table indicat e information specific to a four-layer board. 28 maximum solder temperature 11 lead free (pb-free) leaded (snpb) t sdr ? ? 260.0 245.0 o c 29 moisture sensitivity level 12 msl ? 3 1 functional operating conditions are given in the dc electrical s pecifications. absolute maximum ratings are stress ratings only , and functional operation at the maxima is not guaranteed. stress beyond any of the list ed maxima can affect device reliability or cause permanent damage to the device. 2 1.5 v 10% for proper operation. this parameter is specified at a maximum junction temperature of 150 o c. 3 all functional non-supply i/o pins are clamped to v ss and v dde , or v ddeh . 4 ac signal overshoot and undershoot of up to 2.0 v of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration). 5 internal structures hold the voltage greater than ?1.0 v if the injection current limit of 2 ma is met. keep the negative dc voltage greater than ?0.6 v on sinb during the internal power-on reset (por) state. 6 internal structures hold the input voltage less than the maximum voltage on all pads powered by v ddeh supplies, if the maximum injection current specification is met (2 ma for all pins) and v ddeh is within the operating voltage specifications. 7 internal structures hold the input voltage less than the maximum voltage on all pads powered by v dde supplies, if the maximum injection current specification is met (2 ma for all pins) and v dde is within the operating voltage specifications. 8 total injection current for all pins (including bot h digital and analog) must not exceed 25 ma. 9 total injection current for all analog input pins must not exceed 15 ma. 10 lifetime operation at these specif ication limits is not guaranteed. 11 moisture sensitivity profile per ipc/jedec j-std-020d. 12 moisture sensitivity per jedec test method a112. table 3. MPC5565 thermal characteristics spec MPC5565 thermal characteristic symbol 324 pbga unit 1 junction to ambient 1, 2 , natural convection (one-layer board) 1 junction temperature is a function of on-chip power dissi pation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipat ion of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. r ? ja 29 c/w 2 junction to ambient 1 , 3 , natural convection (four-layer board 2s2p) 3 per jedec jesd51-6 with the board horizontal. r ? ja 19 c/w 3 junction to ambient (@200 ft./min., one-layer board) r ? jma 23 c/w 4 junction to ambient (@200 ft./min., four-layer board 2s2p) r ? jma 16 c/w 5 junction to board 4 (four-layer board 2s2p) 4 thermal resistance between the die and the printed circuit b oard per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. r ? jb 10 c/w 6 junction to case 5 5 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. r ? jc 7c/w 7 junction to package top 6 , natural convection 6 thermal characterization parameter indicati ng the temperature difference between package top and the junction temperature per jedec jesd51-2. ? jt 2c/w table 2. absolute maximum ratings 1 (continued) spec characteristic symbol min. max. unit MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 6 3.2.1 general notes for specifications at maximum junction temperature an estimation of the device junction temperature, t j , can be obtained from the equation: t j = t a + (r ? ja ? p d ) where: t a = ambient temperature for the package ( o c) r ? ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the thermal resistance values used are based on the jedec jesd51 series of standards to provide consistent values for estimations and comparisons. the difference betw een the values determined for the single-layer (1s) board compared to a four-layer boa rd that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal re sistance is not a constant . the thermal resistance depends on the: ? construction of the applicati on board (number of planes) ? effective size of the board which cools the component ? quality of the thermal and elec trical connections to the planes ? power dissipated by adjacent components connect all the ground and powe r balls to the resp ective planes with one via pe r ball. using fewer vias to connect the package to the planes reduces the thermal performance. thinner planes also reduce the thermal performance. when the clearance between the vias le ave the planes virtually disconnected, the thermal performance is also greatly reduced. as a general rule, the value obtaine d on a single-layer board is within the normal range for the tightly packed printed circuit board. the valu e obtained on a board with the intern al planes is usually within the normal range if the application board has: ? one oz. (35 micron nominal thickness) internal planes ? components are well separated ? overall power dissipation on the board is less than 0.02 w/cm 2 the thermal performance of any component depe nds on the power dissipation of the surrounding components. in addition, th e ambient temperature varies widely wi thin the application. for many natural convection and especially closed box applications, the board temperatur e at the perimeter (edge) of the package is approximately the same as the local ai r temperature near the device. specifying the local ambient conditions explicitly as the board temperatur e provides a more precise description of the local ambient conditions that determine the temperature of the device. electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 7 at a known board temperature, th e junction temperature is estima ted using the following equation: t j = t b + (r ? jb ? p d ) where: t j = junction temperature ( o c) t b = board temperature at the package perimeter ( o c/w) r ? jb = junction-to-board thermal resistance ( o c/w) per jesd51-8 p d = power dissipation in the package (w) when the heat loss from the package case to the air doe s not factor into the calcu lation, an acceptable value for the junction temperature is predictable. ensure th e application board is similar to the thermal test condition, with the component soldered to a board with internal planes. the thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient th ermal resistance: r ? ja = r ? jc + r ? ca where: r ? ja = junction-to-ambient thermal resistance ( o c/w) r ? jc = junction-to-case thermal resistance ( o c/w) r ? ca = case-to-ambient thermal resistance ( o c/w) r ? jc is device related and is not affected by other fact ors. the thermal environment can be controlled to change the case-to-ambient thermal resistance, r ? ca . for example, change the air flow around the device, add a heat sink, change the mounti ng arrangement on the printed circui t board, or change the thermal dissipation on the printed circuit board surrounding th e device. this descripti on is most useful for packages with heat sinks where 90% of the heat flow is through th e case to heat sink to ambient. for most packages, a better model is required. a more accurate two-resistor th ermal model can be constructed fr om the junction-to-board thermal resistance and the junction-to-case thermal resistance. the junction-to-case ther mal resistance describes when using a heat sink or where a s ubstantial amount of heat is dissipat ed from the top of the package. the junction-to-board thermal resistan ce describes the thermal performanc e when most of the heat is conducted to the printed circuit board. this model can be used to generate si mple estimations and for computational fluid dynamics (cfd) thermal models. to determine the junction temperature of the devi ce in the application on a prototype board, use the thermal characterization parameter ( ? jt ) to determine the junction temperature by measuring the temperature at the top center of the p ackage case using the following equation: t j = t t + ( ? jt ? p d ) where: t t = thermocouple temperature on top of the package ( o c) ? jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w) MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 8 the thermal characterization parameter is measured in compliance with the je sd51-2 specification using a 40-gauge type t thermoc ouple epoxied to the top center of the package case. position the thermocouple so that the thermocouple junction rests on the package. place a smal l amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. place the thermocouple wire flat against the package case to avoid m easurement errors caused by the co oling effects of the thermocouple wire. references: semiconductor equipment and materials inte rnational 3081 zanker rd. san jose, ca., 95134 (408) 943-6900 mil-spec and eia/jesd (jedec) spec ifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . 1. c.e. triplett and b. joiner, ?an experimental characteri zation of a 272 pbga within an automotive engine controller module,? proceedi ngs of semitherm, san diego, 1998, pp. 47?54. 2. g. kromann, s. shidore, and s. addison, ?therm al modeling of a pbga for air-cooled applica- tions,? electronic packaging and production, pp. 53?58, march 1998. 3. b. joiner and v. adams, ?measu rement and simulation of junction to board thermal resistance and its application in thermal modeling,? pro ceedings of semitherm, san diego, 1999, pp. 212?220. 3.3 package the MPC5565 is available in packaged form. read the package options in section 2, ?ordering information.? refer to section 4, ?mechanicals,? for pinouts and package drawings. 3.4 emi (electromagnetic interference) characteristics table 4. emi testing specifications 1 1 emi testing and i/o port waveforms per sae j1752/3 issued 19 95-03. qualification testing was performed on the mpc5554 and applied to the mpc5500 family as generic emi performance data. spec characteristic minimum typical maximum unit 1 scan range 0.15 ? 1000 mhz 2 operating frequency ? ? f max mhz 3v dd operating voltages ? 1.5 ? v 4v ddsyn , v rc33 , v dd33 , v flash , v dde operating voltages ? 3.3 ? v 5v pp , v ddeh , v dda operating voltages ? 5.0 ? v 6 maximum amplitude ? ? 14 2 32 3 2 measured with the single-chip emi program. 3 measured with the expanded emi program. dbuv 7 operating temperature ? ? 25 o c electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 9 3.5 esd (electromagnetic stat ic discharge) characteristics 3.6 voltage regulator controller (v rc ) and power-on reset (por) electrical specifications the following table lists the v rc and por electrical specifications: table 5. esd ratings 1, 2 1 all esd testing conforms to cdf-aec -q100 stress test qualification for automotive grade integrated circuits. 2 device failure is defined as: ?if after exposure to esd pulses, the device does not meet the device specification requirements, which includes the complete dc parametric and function al testing at room temper ature and hot temperature. characteristic symbol value unit esd for human body model (hbm) 2000 v hbm circuit description r1 1500 ? c100 pf esd for field induced charge model (fdcm) 500 (all pins) v 750 (corner pins) number of pulses per pin: positive pulses (hbm) negative pulses (hbm) ? ? 1 1 ? ? interval of pulses ? 1 second table 6. v rc and por electrical specifications spec characteristic symbol min. max. units 11.5 v (v dd ) por 1 negated (ramp up) asserted (ramp down) v por15 1.1 1.1 1.35 1.35 v 23.3 v (v ddsyn ) por 1 asserted (ramp up) negated (ramp up) asserted (ramp down) negated (ramp down) v por33 0.0 2.0 2.0 0.0 0.30 2.85 2.85 0.30 v 3 reset pin supply (v ddeh6 ) por 1, 2 negated (ramp up) asserted (ramp down) v por5 2.0 2.0 2.85 2.85 v 4 v rc33 voltage before v rc allows the pass transistor to start turning on v trans_start 1.0 2.0 v 5 when v rc allows the pass transistor to completely turn on 3, 4 v trans_on 2.0 2.85 v 6 when the voltage is greater than the voltage at which the v rc keeps the 1.5 v supply in regulation 5, 6 v vrc33reg 3.0 ? v current can be sourced ?40 o c11.0?ma 7 by v rcctl at tj: 25 o ci vrcctl 7 9.0 ? ma 150 o c 7.5 ? ma 8 voltage differential during power up such that: v dd33 can lag v ddsyn or v ddeh6 before v ddsyn and v ddeh6 reach the v por33 and v por5 minimums respectively. v dd33_lag ?1.0v MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 10 3.7 power-up/down sequencing power sequencing between th e 1.5 v power supply and v ddsyn or the reset power supplies is required if using an external 1.5 v power supply with v rc33 tied to ground (gnd). to avoid power-sequencing, v rc33 must be powered up within the specified operati ng range, even if the on-chip voltage regulator controller is not used. refer to section 3.7.2, ?power-up sequence (vrc33 grounded) , ? and section 3.7.3, ?power-down sequence (vrc33 grounded) . ? power sequencing requires that v dd33 must reach a certain voltage where the values are read as ones before the por signal negates. refer to section 3.7.1, ?input value of pins during por dependent on vdd33 . ? although power sequencing is not required between v rc33 and v ddsyn during power up, v rc33 must not lead v ddsyn by more than 600 mv or lag by more than 100 mv for the v rc stage turn-on to operate within specification. higher spikes in the emitte r current of the pass transistor occur if v rc33 leads or lags v ddsyn by more than these amounts. the value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. furthermore, when all of the pors negate, the system clock starts to toggle, adding another large increase of the current consumed by v rc33 . if v rc33 lags v ddsyn by more than 100 mv, the increase in current consumed can drop v dd low enough to assert the 1.5 v por again. oscillations are possible when the 1.5 v por asserts and stops the syst em clock, causing the voltage on v dd to rise until the 1.5 v por negates again. all osci llations stop when v rc33 is powered sufficiently. 9 absolute value of slew rate on power supply pins ? ? 50 v/ms 10 required gain at tj: i dd ? i vrcctl (@ f sys = f max ) 6 , 7 , 8, 9 ? 40 o c beta 10 40 ? ? 25 o c45?? 150 o c 55 500 ? 1 the internal por signals are v por15 , v por33 , and v por5 . on power up, assert reset before the internal por negates. reset must remain asserted until the power supplies ar e within the operating conditions as specified in ta b l e 9 dc electrical specifications. on power down, assert reset before any power supplies fall outside the operating conditions and until the internal por asserts. 2 v il_s ( ta b l e 9 , spec15) is guaranteed to scale with v ddeh6 down to v por5 . 3 supply full operating current for the 1.5 v supp ly when the 3.3 v supply reaches this range. 4 it is possible to reach the current limit during ramp up?do not treat this event as short circuit current. 5 at peak current for device. 6 requires compliance with freescale?s recommended board r equirements and transistor recommendations. board signal traces/routing from the v rcctl package signal to the base of the external pa ss transistor and between the emitter of the pass transistor to the v dd package signals must have a maximum of 100 nh inductance and minimal resistance (less than 1 ? ). v rcctl must have a nominal 1 ? f phase compensation capacitor to ground. v dd must have a 20 ? f (nominal) bulk capacitor (greater than 4 ? f over all conditions, including lifetime). place high-frequency bypass capacitors consisting of eight 0.01 ? f, two 0.1 ? f, and one 1 ? f capacitors around the package on the v dd supply signals. 7 i vrcctl is measured at the following conditions: v dd = 1.35 v, v rc33 = 3.1 v, v vrcctl = 2.2 v. 8 refer to ta b l e 1 for the maximum operating frequency. 9 values are based on i dd from high-use applications as explained in the i dd electrical specification. 10 beta is the worst-case external transistor beta. it is measured on a per-part basis and calculated as (i dd ? i vrcctl ). table 6. v rc and por electrical specifications (continued) spec characteristic symbol min. max. units electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 11 when powering down, v rc33 and v ddsyn have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. wh en not powering up or down, no delta between v rc33 and v ddsyn is required for the v rc to operate within specification. there are no power up/down sequencing requirements to prevent issues su ch as latch-up, excessive current spikes, and so on. therefore, the state of the i/o pins during power up and power down varies depending on which supplies are powered. table 7 gives the pin state for the sequence cases fo r all pins with pad type pad_fc (fast type). table 8 gives the pin state for the sequence cases for a ll pins with pad type pad_mh (medium type) and pad_sh (slow type). the values in table 7 and table 8 do not include the effect of the weak-pull devices on the output pins during power up. before exiting the internal por state, the voltage on the pins go to a high-im pedance state until por negates. when the internal por negates, the functi onal state of the signal during reset applies and the weak-pull devices (up or down) are enabled as defined in the device reference manual. if v dd is too low to correctly propagate the logic signals , the weak-pull devices can pull the signals to v dde and v ddeh . to avoid this condition, minimize the ramp time of the v dd supply to a time period less than the time required to enable the external circ uitry connected to the device outputs. during initial power ramp-up, when vstby is 0.6v or above. a typical cu rrent of 1-3ma and maximum of 4ma may be seen until v dd is applied. this current will not reoccur until v stby is lowered below v stby min. specification. table 7. pin status for fast pads during the power sequence v dde v dd33 v dd por pin status for fast pad output driver pad_fc (fast) low ? ? asserted low v dde low low asserted high v dde low v dd asserted high v dde v dd33 low asserted high impedance (hi-z) v dde v dd33 v dd asserted hi-z v dde v dd33 v dd negated functional table 8. pin status for medium and slow pads during the power sequence v ddeh v dd por pin status for medium and slow pad output driver pad_mh (medium) pad_sh (slow) low ? asserted low v ddeh low asserted high impedance (hi-z) v ddeh v dd asserted hi-z v ddeh v dd negated functional MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 12 figure 2 shows an approximate interpolation of the i stby worst-case specification to estimate values at different voltages and temperatures . the vertical li nes shown at 25 ? c, 60 ? c, and 150 ? c in figure 2 are the actual i dd_stby specifications (27d) listed in table 9 . figure 2. fi stby worst-case specifications electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 13 3.7.1 input value of pins during por dependent on v dd33 when powering up the device, v dd33 must not lag the latest v ddsyn or reset power pin (v ddeh6 ) by more than the v dd33 lag specification listed in table 6 , spec 8. this avoids accidentally selecting the bypass clock mode because the internal versions of pllcfg[0:1] and rstcfg are not powered and therefore cannot read the defaul t state when por negates. v dd33 can lag v ddsyn or the reset power pin (v ddeh6 ), but cannot lag both by more than the v dd33 lag specification. this v dd33 lag specification applies during power up only. v dd33 has no lead or lag requirements when powering down. 3.7.2 power-up sequence (v rc33 grounded) the 1.5 v v dd power supply must rise to 1.35 v before the 3.3 v v ddsyn power supply and the reset power supply rises above 2.0 v. this ensures that di gital logic in the pll fo r the 1.5 v power supply does not begin to operate below the spec ified operation range lower limit of 1.35 v. because the internal 1.5 v por is disabled, the internal 3.3 v por or the reset power por must hold th e device in reset. since they can negate as low as 2.0 v, v dd must be within specification be fore the 3.3 v por and the reset por negate. figure 3. power-up sequence (v rc33 grounded) 3.7.3 power-down sequence (v rc33 grounded) the only requirement for the power-down sequence with v rc33 grounded is if v dd decreases to less than its operating range, v ddsyn or the reset power must decrease to less than 2.0 v before the v dd power increases to its operating range. this ensures that the digital 1.5 v logic, which is reset only by an ored por and can cause the 1.5 v supply to decrease less than its specification valu e, resets correctly. see table 6 , footnote 1. v ddsyn and reset power v dd 2.0 v 1.35 v v dd must reach 1.35 v before v ddsyn and the reset power reach 2.0 v MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 14 3.8 dc electrical specifications table 9. dc electrical specifications (t a = t l to t h ) spec characteristic symbol min max. unit 1 core supply voltage (average dc rms voltage) v dd 1.35 1.65 v 2 input/output supply volt age (fast input/output) 1 v dde 1.62 3.6 v 3 input/output supply voltage (s low and medium input/output) v ddeh 3.0 5.25 v 4 3.3 v input/output buffer voltage v dd33 3.0 3.6 v 5 voltage regulator control input voltage v rc33 3.0 3.6 v 6 analog supply voltage 2 v dda 4.5 5.25 v 8 flash programming voltage 3 v pp 4.5 5.25 v 9 flash read voltage v flash 3.0 3.6 v 10 sram standby voltage 4 v stby 0.8 1.2 v 11 clock synthesizer operating voltage v ddsyn 3.0 3.6 v 12 fast i/o input high voltage v ih_f 0.65 ? v dde v dde + 0.3 v 13 fast i/o input low voltage v il_f v ss ? 0.3 0.35 ? v dde v 14 medium and slow i/o input high voltage v ih_s 0.65 ? v ddeh v ddeh + 0.3 v 15 medium and slow i/o input low voltage v il_s v ss ? 0.3 0.35 ? v ddeh v 16 fast input hysteresis v hys_f 0.1 ? v dde v 17 medium and slow i/o input hysteresis v hys_s 0.1 ? v ddeh v 18 analog input voltage v indc v ssa ? 0.3 v dda + 0.3 v 19 fast output high voltage (i oh_f = ?2.0 ma) v oh_f 0.8 ? v dde ?v 20 slow and medium output high voltage i oh_s = ?2.0 ma i oh_s = ?1.0 ma v oh_s 0.80 ? v ddeh 0.85 ? v ddeh ?v 21 fast output low voltage (i ol_f = 2.0 ma) v ol_f ?0.2 ? v dde v 22 slow and medium output low voltage i ol_s = 2.0 ma i ol_s = 1.0 ma v ol_s ? 0.20 ? v ddeh 0.15 ? v ddeh v 23 load capacitance (fast i/o) 5 dsc (siu_pcr[8:9]) = 0b00 = 0b01 = 0b10 = 0b11 c l ? ? ? ? 10 20 30 50 pf pf pf pf 24 input capacitance (digital pins) c in ?7pf 25 input capacitance (analog pins) c in_a ?10pf 26 input capacitance: (shared digital and analog pins an[12]_ma[0]_sds , an[13]_ma[1]_sdo, an[14]_ma[2]_sdi, and an[15]_fck) c in_m ?12pf electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 15 27a operating current 1.5 v supplies @ 135 mhz: 6 v dd (including v ddf max current) @1.65 v typical use 7, 8 v dd (including v ddf max current) @1.35 v typical use 7 , 8 v dd (including v ddf max current) @1.65 v high use 8 , 9 v dd (including v ddf max current) @1.35 v high use 8 , 9 i dd i dd i dd i dd ? ? ? ? 460 10 360 10 510 10 410 10 ma ma ma ma 27b operating current 1.5 v supplies @ 114 mhz: 6 v dd (including v ddf max current)@1.65 v typical use 7 , 8 v dd (including v ddf max current) @1.35 v typical use 7 , 8 v dd (including v ddf max current) @1.65 v high use 8 , 9 v dd (including v ddf max current) @1.35 v high use 8 , 9 i dd i dd i dd i dd ? ? ? ? 410 10 310 10 460 10 370 10 ma ma ma ma 27c operating current 1.5 v supplies @ 82 mhz: 6 v dd (including v ddf max current) @1.65 v typical use 7 , 8 v dd (including v ddf max current) @1.35 v typical use 7 , 8 v dd (including v ddf max current) @1.65 v high use 8 , 9 v dd (including v ddf max current) @1.35 v high use 8 , 9 i dd i dd i dd i dd ? ? ? ? 330 10 225 10 385 10 290 10 ma ma ma ma 27d ram standby current. 11 i dd_stby @ 25 o c v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v i dd_stby @ 60 o c v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v i dd_stby @ 150 o c (tj) v stby @ 0.8 v v stby @ 1.0 v v stby @ 1.2 v i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby i dd_stby ? ? ? ? ? ? ? ? ? 20 30 50 70 100 200 1200 1500 2000 ? a ? a ? a ? a ? a ? a ? a ? a ? a 28 operating current 3.3 v supplies @ f max mhz v dd33 12 i dd_33 ? 2 + (values derived from procedure of footnote 12 ) ma v flash i vflash ?10ma v ddsyn i ddsyn ?15ma 29 operating current 5.0 v supplies (12 mhz adclk): v dda (v dda0 + v dda1 ) analog reference supply current (v rh , v rl ) v pp i dd_a i ref i pp ? ? ? 20.0 1.0 25.0 ma ma ma table 9. dc electrical specifications (t a = t l to t h ) (continued) spec characteristic symbol min max. unit MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 16 30 operating current v dde supplies: 13 v ddeh1 v dde2 v dde3 v ddeh4 v dde5 v ddeh6 v dde7 v ddeh8 v ddeh9 i dd1 i dd2 i dd3 i dd4 i dd5 i dd6 i dd7 i dd8 i dd9 ? ? ? ? ? ? ? ? ? refer to footnote 13 ma ma ma ma ma ma ma ma ma 31 fast i/o weak pullup current 14 1.62?1.98 v 2.25?2.75 v 3.00?3.60 v i act_f 10 20 20 110 130 170 ? a ? a ? a fast i/o weak pulldown current 14 1.62?1.98 v 2.25?2.75 v 3.00?3.60 v 10 20 20 100 130 170 ? a ? a ? a 32 slow and medium i/o weak pullup/down current 14 3.0?3.6 v 4.5?5.5 v i act_s 10 20 150 170 ? a ? a 33 i/o input leakage current 15 i inact_d ?2.5 2.5 ? a 34 dc injection current (per pin) i ic ?2.0 2.0 ma 35 analog input current, channel off 16 i inact_a ?150 150 na 35a analog input current, shared analog / digital pins (an[12], an[13], an[14], an[15]) i inact_ad ?2.5 2.5 ? a 36 v ss to v ssa differential voltage 17 v ss ? v ssa ?100 100 mv 37 analog reference low voltage v rl v ssa ? 0.1 v ssa + 0.1 v 38 v rl differential voltage v rl ? v ssa ?100 100 mv 39 analog reference high voltage v rh v dda ? 0.1 v dda + 0.1 v 40 v ref differential voltage v rh ? v rl 4.5 5.25 v 41 v sssyn to v ss differential voltage v sssyn ? v ss ?50 50 mv 42 v rcvss to v ss differential voltage v rcvss ? v ss ?50 50 mv 43 v ddf to v dd differential voltage v ddf ? v dd ?100 100 mv 43a v rc33 to v ddsyn differential voltage v rc33 ? v ddsyn ?0.1 0.1 18 v 44 analog input differential signal range (with common mode 2.5 v) v idiff ?2.5 2.5 v 45 operating temperature ra nge, ambient (packaged) t a = (t l to t h )t l t h ? c 46 slew rate on power-supply pins ? ? 50 v/ms 1 v dde2 and v dde3 are limited to 2.25?3.6 v on ly if siu_eccr[ebts] = 0; v dde2 and v dde3 have a range of 1.6?3.6 v if siu_eccr[ebts] = 1. table 9. dc electrical specifications (t a = t l to t h ) (continued) spec characteristic symbol min max. unit electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 17 2 | v dda0 ? v dda1 | must be < 0.1 v. 3 v pp can drop to 3.0 v during read operations. 4 if standby operation is not required, connect v stby to ground. 5 applies to clkout, external bus pins, and nexus pins. 6 maximum average rms dc current. 7 average current measured on automotive benchmark. 8 peak currents can be higher on specialized code. 9 high use current measured while running optimized spe asse mbly code with all code and data 100% locked in cache (0% miss rate) with all channels of the emios and etpu running au tonomously, plus the edma transfe rring data continuously from sram to sram. higher currents can occur if an ?idle? loop that crosses cache lines is run from cache. design and write code to avoid this condition. 10 final values listed in specs 27a ?27c are based on characterization. 11 the current specification relates to aver age standby operation after sram has been loaded with data. for power up current see section 3.7, ?power-up/down sequencing ?, figure 2 . 12 power requirements for the v dd33 supply depend on the frequency of operation, load of all i/o pins, and the voltages on the i/o segments. refer to ta b l e 1 1 for values to calculate the power dissipation for a specific operation. 13 power requirements for each i/o segment ar e dependent on the frequency of operation and load of the i/o pins on a particular i/ o segment, and the voltage of the i/o segment. refer to ta b l e 1 0 for values to calculate power diss ipation for specific operation. the total power consumption of an i/o segment is the sum of th e individual power consumptions for each pin on the segment. 14 absolute value of current, measured at v il and v ih . 15 weak pullup/down inactive. measured at v dde = 3.6 v and v ddeh = 5.25 v. applies to pad types: pad_fc, pad_sh, and pad_mh. 16 maximum leakage occurs at maximum operating temperature. leakage current decreases by approximately one-half for each 8 o c to 12 o c, in the ambient temperature range of 50 o c to 125 o c. applies to pad types: pad_a and pad_ae. 17 v ssa refers to both v ssa0 and v ssa1 . | v ssa0 ? v ssa1 | must be < 0.1 v. 18 up to 0.6 v during power up and power down. MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 18 3.8.1 i/o pad current specifications the power consumption of an i/o se gment depends on the usage of the pi ns on a particular segment. the power consumption is the sum of al l output pin currents for a segmen t. the output pin current can be calculated from table 10 based on the voltage, frequency, and lo ad on the pin. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 10 . table 10. i/o pad average dc current (t a = t l to t h ) 1 1 these values are estimates from simulation and ar e not tested. currents apply to output pins only. spec pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. voltag e (v) drive select / slew rate control setting current (ma) 1 slow i drv_sh 25 50 5.25 11 8.0 210505.25013.2 3 2 50 5.25 00 0.7 4 2 200 5.25 00 2.4 5 medium i drv_mh 50 50 5.25 11 17.3 620505.25016.5 7 3.33 50 5.25 00 1.1 8 3.33 200 5.25 00 3.9 9 fast i drv_fc 66 10 3.6 00 2.8 10 66 20 3.6 01 5.2 11 66 30 3.6 10 8.5 12 66 50 3.6 11 11.0 13 66 10 1.98 00 1.6 14 66 20 1.98 01 2.9 15 66 30 1.98 10 4.2 16 66 50 1.98 11 6.7 17 56 10 3.6 00 2.4 18 56 20 3.6 01 4.4 19 56 30 3.6 10 7.2 20 56 50 3.6 11 9.3 21 56 10 1.98 00 1.3 22 56 20 1.98 01 2.5 23 56 30 1.98 10 3.5 24 56 50 1.98 11 5.7 25 40 10 3.6 00 1.7 26 40 20 3.6 01 3.1 27 40 30 3.6 10 5.1 28 40 50 3.6 11 6.6 29 40 10 1.98 00 1.0 30 40 20 1.98 01 1.8 31 40 30 1.98 10 2.5 32 40 50 1.98 11 4.0 electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 19 3.8.2 i/o pad v dd33 current specifications the power consumption of the v dd33 supply dependents on the usage of the pins on all i/o segments. the power consumption is the sum of all input and output pin v dd33 currents for all i/ o segments. the output pin v dd33 current can be calculated from table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. the input pin v dd33 current can be calculated from table 11 based on the voltage, frequency, and load on all pad_sh and pad_mh pins. use li near scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 11 . table 11. v dd33 pad average dc current (t a = t l to t h ) 1 1 these values are estimated from simulation and not tested. currents apply to output pins for the fast pads only and to input pins for the slow and medium pads only. spec pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. v dd33 (v) v dde (v) drive select current (ma) inputs 1slowi 33_sh 66 0.5 3.6 5.5 na 0.003 2 medium i 33_mh 66 0.5 3.6 5.5 na 0.003 outputs 3 fast i 33_fc 66 10 3.6 3.6 00 0.35 466203.63.6010.53 566303.63.6100.62 666503.63.6110.79 7 66 10 3.6 1.98 00 0.35 8 66 20 3.6 1.98 01 0.44 9 66 30 3.6 1.98 10 0.53 10 66 50 3.6 1.98 11 0.70 11 56 10 3.6 3.6 00 0.30 12 56 20 3.6 3.6 01 0.45 13 56 30 3.6 3.6 10 0.52 14 56 50 3.6 3.6 11 0.67 15 56 10 3.6 1.98 00 0.30 16 56 20 3.6 1.98 01 0.37 17 56 30 3.6 1.98 10 0.45 18 56 50 3.6 1.98 11 0.60 19 40 10 3.6 3.6 00 0.21 20 40 20 3.6 3.6 01 0.31 21 40 30 3.6 3.6 10 0.37 22 40 50 3.6 3.6 11 0.48 23 40 10 3.6 1.98 00 0.21 24 40 20 3.6 1.98 01 0.27 25 40 30 3.6 1.98 10 0.32 26 40 50 3.6 1.98 11 0.42 MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 20 3.9 oscillator and fmpll electrical characteristics table 12. fmpll electrical specifications (v ddsyn = 3.0?3.6 v; v ss = v sssyn = 0.0 v; t a = t l to t h ) spec characteristic symb ol minimum maximum unit 1 pll reference frequency range: 1 crystal reference 2 external reference 2 dual controller (1:1 mode) f ref_crystal f ref_ext f ref_1:1 8 8 24 20 20 f sys ? 2 mhz 2 system frequency 3 f sys f ico ( min ) ? 2 rfd f max 4 mhz 3 system clock period t cyc ?1 ? f sys ns 4 loss of reference frequency 5 f lor 100 1000 khz 5 self-clocked mode (scm) frequency 6 f scm 7.4 17.5 mhz 6 extal input high voltage crystal mode 7 all other modes [dual controller (1:1), bypass, external reference] v ihext v ihext v xtal + 0.4 v (v dde5 ? 2) + 0.4 v ? ? v v 7 extal input low voltage crystal mode 8 all other modes [dual controller (1:1), bypass, external reference] v ilext v ilext ? ? v xtal ? 0.4 v (v dde5 ?? 2) ? 0.4 v v v 8xtal current 9 i xtal 26ma 9 total on-chip stray capacitance on xtal c s_xtal ?1.5pf 10 total on-chip stray capacitance on extal c s_extal ?1.5pf 11 crystal manufacturer?s recommended capacitive load c l refer to crystal specification refer to crystal specification pf 12 discrete load capacitance to connect to extal c l_extal ? (2 ? c l ) ? c s_extal ? c pcb_extal 10 pf 13 discrete load capacitance to connect to xtal c l_xtal ? (2 ? c l ) ? c s_xtal ? c pcb_xtal 10 pf 14 pll lock time 11 t lpll ? 750 ? s 15 dual controller (1:1) clock skew (between clkout and extal) 12, 13 t skew ?2 2 ns 16 duty cycle of reference t dc 40 60 % 17 frequency unlock range f ul ?4.0 4.0 % f sys 18 frequency lock range f lck ?2.0 2.0 % f sys electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 21 19 clkout period jitter, measured at f sys max: 14, 15 peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over a 2 ms interval) c jitter ? ? 5.0 0.01 % f clkout 20 frequency modulation range limit 16 (do not exceed f sys maximum) c mod 0.8 2.4 %f sys 21 ico frequency f ico = [f ref_crystal ? (mfd + 4)] ?? (prediv + 1) 17 f ico = [f ref_ext ? (mfd + 4)] ?? (prediv + 1) f ico 48 f max mhz 22 predivider output frequency (to pll) f prediv 420 18 mhz 1 nominal crystal and external reference values are worst-case not more than 1%. the device operates correctly if the frequency remains within 5% of the specification limit. this tolerance r ange allows for a slight frequency drift of the crystals over t ime. the designer must thoroughly understand the drift margin of the source clock. 2 the 8?20 mhz crystal or external reference values have pllcfg[2] pulled low. pllcfg[2] is not supported pulled high. 3 all internal registers retain data at 0 hz. 4 up to the maximum frequency rating of the device (refer to ta b l e 1 ). 5 loss of reference frequency is defined as the reference frequency detected internally, which transitions the pll into self-cloc ked mode. 6 the pll operates at self-clocked mode (scm) frequency when the reference frequency falls below f lor . scm frequency is measured on the clkout ball wit h the divider set to divide-b y-two of the system clock. note: in scm, the mfd and prediv have no effect and the rfd is bypassed. 7 use the extal input high voltage parameter when using the fl excan oscillator in crystal mode (no quartz crystals or resonators). (v extal ? v xtal ) must be ? 400 mv for the oscillator?s compar ator to produce the output clock. 8 use the extal input low voltage parameter when using the flexcan oscillator in crystal mode (no quartz crystals or resonators). (v xtal ?v extal ) must be ? 400 mv for the oscillator?s compar ator to produce the output clock. 9 i xtal is the oscillator bias curr ent out of the xtal pin with both extal and xtal pins grounded. 10 c pcb_extal and c pcb_xtal are the measured pcb stray capacitances on extal and xtal, respectively. 11 this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). from power up with crysta l oscillator reference, the lock time also includes the crystal startup time. 12 pll is operating in 1:1 pll mode. 13 v dde = 3.0?3.6 v. 14 jitter is the average deviation from t he programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device po wered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v sssyn and variation in crystal oscillator frequency increase the jitter percentage for a given interval. clkout divider is set to divide-by-two. 15 values are with frequency modulation disabled. if frequency m odulation is enabled, jitter is the sum of (jitter + cmod). 16 modulation depth selected must not result in f sys value greater than the f sys maximum specified value. 17 f sys = f ico ? (2 rfd ). 18 maximum value for dual controller (1:1) mode is (f max ?? 2) with the predivider set to 1 (fmpll_syncr[prediv] = 0b001). table 12. fmpll electrical specifications (continued) (v ddsyn = 3.0?3.6 v; v ss = v sssyn = 0.0 v; t a = t l to t h ) spec characteristic symb ol minimum maximum unit MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 22 3.10 eqadc electrical characteristics table 13. eqadc conversion specifications ( t a = t l to t h ) spec characteristic symbol minimum maximum unit 1 adc clock (adclk) frequency 1 1 conversion characteristics vary with f adclk rate. reduced conversion accuracy occurs at maximum f adclk rate. the maximum value is based on 800 ks/s and the minimum value is based on 20 mhz oscillator clock frequency divided by a maximum 16 factor. f adclk 112mhz 2 conversion cycles differential single ended cc 13 + 2 (15) 14 + 2 (16) 13 + 128 (141) 14 + 128 (142) adclk cycles 3 stop mode recovery time 2 2 stop mode recovery time begins when the adc control register enable bits are set until the adc is ready to perform conversions. t sr 10 ? ? s 4 resolution 3 3 at v rh ? v rl = 5.12 v, one least significant bit (lsb) = 1.25, mv = one count. ?1.25 ? mv 5 inl: 6 mhz adc clock inl6 ?4 4 counts 3 6 inl: 12 mhz adc clock inl12 ?8 8 counts 7 dnl: 6 mhz adc clock dnl6 ?3 4 4 guaranteed 10-bit mono tonicity. 3 4 counts 8 dnl: 12 mhz adc clock dnl12 ?6 4 6 4 counts 9 offset error with calibration offwc ?4 5 5 the absolute value of the offset error without calibration ? 100 counts. 4 5 counts 10 full-scale gain error with calibration gainwc ?8 6 6 the absolute value of the full scale gain error without calibration ? 120 counts. 8 6 counts 11 disruptive input injection current 7, 8, 9, 10 7 below disruptive current conditions, the channel being stressed has conversion values of: 0x3ff for analog inputs greater than v rh , and 0x000 for values less than v rl . this assumes that v rh ? v dda and v rl ? v ssa due to the presence of the sample amplifier. other channels are not af fected by non-disruptive conditions. 8 exceeding the limit can cause a conversion error on both stressed and unstressed channels. transi tions within the limit do not affect device reliability or cause permanent damage. 9 input must be current limited to the val ue specified. to determine the value of th e required current-limiting resistor, calcula te resistance values using v posclamp = v dda + 0.5 v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 10 this condition applies to two adjacent pads on the internal pad. i inj ?1 1 ma 12 incremental error due to injection current. all channels are 10 k ? < rs <100 k ? channel under test has rs = 10 k ? , i inj = i injmax , i injmin e inj ?4 4 counts 13 total unadjusted error (tue) for single ended conversions with calibration 11, 12, 13, 14, 15 11 the tue specification is always less t han the sum of the inl, dn l, offset, and gain errors due to canceling errors. 12 tue does not apply to differential conversions. 13 measured at 6 mhz adc clock. tue with a 12 mhz adc clock is: ?16 counts < tue < 16 counts. 14 tue includes all internal device errors such as internal reference variation (75% ref, 25% ref). 15 depending on the input impedance, the analog input leakage current ( ta b l e 9 . dc electrical specifications, spec 35a) can affect the actual tue measured on analog channels an[12], an[13], an[14], an[15]. tue ?4 4 counts electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 23 3.11 h7fa flash memory electrical characteristics table 14. flash program and erase specifications (t a = t l to t h ) spec flash program characte ristic symbol min. typical 1 1 typical program and erase times are calculated at 25 o c operating temperature using nominal supply values. initial max. 2 2 initial factory condition: ?? 100 ? program/erase cycles, 25 o c, using a typical supply voltage measured at a minimum system frequency of 80 mhz. max. 3 3 the maximum erase time occurs after the specified number of program/erase cycles. this maximum value is characterized but not guaranteed. unit 3 doubleword (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. t dwprogram ? 10 ? 500 ? s 4 page program time 4 t pprogram ? 22 44 5 5 page size is 256 bits (8 words). 500 ? s 7 16 kb block pre-program and erase time t 16kpperase ? 265 400 5000 ms 9 48 kb block pre-program and erase time t 48kpperase ? 345 400 5000 ms 10 64 kb block pre-program and erase time t 64kpperase ? 415 500 5000 ms 8 128 kb block pre-program and erase time t 128kpperase ? 500 1250 7500 ms 11 minimum operating frequency for program and erase operations 6 6 the read frequency of the flash can range up to the maxi mum operating frequency. there is no minimum read frequency condition. ?25???mhz table 15. flash eeprom module life (t a = t l to t h ) spec characteristic symbol min. typical 1 1 typical endurance is evaluated at 25 o c. product qualification is performed to the minimum specification. for additional information on the freescale definition of typical endurance , refer to engineering bulletin eb619 typical endurance for nonvolatile memory. unit 1a number of program/erase cycles per block for 16 kb, 48 kb, and 64 kb blocks over the operating temperature range (t j ) p/e 100,000 ? cycles 1b number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) p/e 1000 100,000 cycles 2 data retention blocks with 0? 1,000 p/e cycles blocks with 1,00 1?100,000 p/e cycles retention 20 5 ? ? years MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 24 table 16 shows the flash_biu settings versus frequency of operation. refer to the device reference manual for definitions of these bit fields. 3.12 ac specifications 3.12.1 pad ac specifications table 16. flash_biu settings vs. frequency of operation 1 1 illegal combinations exist. use entries from the same row in this table. maximum frequency (mhz) apc rwsc wwsc dpfen 2 2 for maximum flash performance, set to 0b11. ipfen 2 pflim 3 3 for maximum flash performance, set to 0b110. bfen 4 4 for maximum flash performance, set to 0b1. up to and including 82 mhz 5 5 82 mhz parts allow for 80 mhz system clock + 2% frequency modulation (fm). 0b001 0b001 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 up to and including 102 mhz 6 6 102 mhz parts allow for 100 mhz system clock + 2% fm. 0b001 0b010 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 up to and including 135 mhz 7 7 135 mhz parts allow for 132 mhz system clock + 2% fm. 0b010 0b011 0b01 0b00 0b01 0b11 0b00 0b01 0b11 0b000 to 0b110 0b0 0b1 default setting after reset 0b111 0b111 0b11 0b00 0b00 0b000 0b0 table 17. pad ac specifications (v ddeh = 5.0 v, v dde = 1.8 v) 1 spec pad src / dsc (binary) out delay 2, 3, 4 (ns) rise / fall 4 , 5 (ns) load drive (pf) 1 slow high voltage (sh) 11 26 15 50 82 60 200 01 75 40 50 137 80 200 00 377 200 50 476 260 200 2 medium high voltage (mh) 11 16 8 50 43 30 200 01 34 15 50 61 35 200 00 192 100 50 239 125 200 electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 25 3fast 00 3.1 2.7 10 01 2.5 20 10 2.4 30 11 2.3 50 4 pullup/down (3.6 v max) ? ? 7500 50 5 pullup/down (5.5 v max) ? ? 9000 50 1 these are worst-case values that are estimated from simulati on (not tested). the values in the table are simulated at: v dd = 1.35?1.65 v; v dde = 1.62?1.98 v; v ddeh = 4.5?5.25 v; v dd33 and v ddsyn = 3.0?3.6 v; and t a =t l to t h . 2 this parameter is supplied for reference and is guaranteed by design (not tested). 3 the output delay is shown in figure 4 . to calculate the output delay with respect to the system clock, add a maximum of one system clock to the output delay. 4 the output delay and rise and fall are measured to 20% or 80% of the respective signal. 5 this parameter is guaranteed by characterization rather than 100% tested. table 18. derated pad ac specifications (v ddeh = 3.3 v, v dde = 3.3 v) 1 1 these are worst-case values that are es timated from simulation (not tested). the values in the table are simulated at: v dd = 1.35?1.65 v; v dde = 3.0?3.6 v; v ddeh = 3.0?3.6 v; v dd33 and v ddsyn = 3.0?3.6 v; and t a = t l to t h . spec pad src/dsc (binary) out delay 2, 3, 4 (ns) 2 this parameter is supplied for referenc e and guaranteed by design (not tested). rise / fall 3 , 5 (ns) load drive (pf) 1 slow high voltage (sh) 11 39 23 50 120 87 200 01 101 52 50 188 111 200 00 507 248 50 597 312 200 2 medium high voltage (mh) 11 23 12 50 64 44 200 01 50 22 50 90 50 200 00 261 123 50 305 156 200 3fast 00 3.2 2.4 10 01 2.2 20 10 2.1 30 11 2.1 50 4 pullup/down (3.6 v max) ? ? 7500 50 5 pullup/down (5.5 v max) ? ? 9500 50 table 17. pad ac specifications (v ddeh = 5.0 v, v dde = 1.8 v) 1 (continued) spec pad src / dsc (binary) out delay 2, 3, 4 (ns) rise / fall 4 , 5 (ns) load drive (pf) MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 26 figure 4. pad output delay 3.13 ac timing 3.13.1 reset and configuration pin timing 3 the output delay, and the rise and fall, are calcul ated to 20% or 80% of the respective signal. 4 the output delay is shown in figure 4 . to calculate the output dela y with respect to the system clock, add a maximum of one system clock to the output delay. 5 this parameter is guaranteed by charac terization rather than 100% tested. table 19. reset and configuration pin timing 1 1 reset timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . spec characteristic symbol min. max. unit 1 reset pulse width t rpw 10 ? t cyc 2 reset glitch detect pulse width t gpw 2?t cyc 3 pllcfg, bootcfg, wkpcfg, rstcfg setup time to rstout valid t rcsu 10 ? t cyc 4 pllcfg, bootcfg, wkpcfg, rstcfg hold time from rstout valid t rch 0?t cyc v dd ?? 2 v oh v ol rising-edge out delay falling-edge pad internal data pad output out delay input signal electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 27 figure 5. reset and configuration pin timing 3.13.2 ieee 1149.1 interface timing table 20. jtag pin ac electrical characteristics 1 1 these specifications apply to jtag boundary scan only. jtag timing specified at: v dde = 3.0?3.6 v and t a = t l to t h . refer to ta b l e 2 1 for nexus specifications. spec characteristic symbol min. max. unit 1 tck cycle time t jcyc 100 ? ns 2 tck clock pulse width (measured at v dde ? 2) t jdc 40 60 ns 3 tck rise and fall times (40% to 70%) t tckrise ?3ns 4 tms, tdi data setup time t tmss, t tdis 5?ns 5 tms, tdi data hold time t tmsh, t tdih 25 ? ns 6 tck low to tdo data valid t tdov ?20ns 7 tck low to tdo data invalid t tdoi 0?ns 8 tck low to tdo high impedance t tdohz ?20ns 9 jcomp assertion time t jcmppw 100 ? ns 10 jcomp setup time to tck low t jcmps 40 ? ns 11 tck falling-edge to output valid t bsdv ?50ns 12 tck falling-edge to output valid out of high impedance t bsdvz ?50ns 13 tck falling-edge to output high impedance (hi-z) t bsdhz ?50ns 14 boundary scan input valid to tck rising-edge t bsdst 50 ? ns 15 tck rising-edge to boundary scan input invalid t bsdht 50 ? ns 1 2 reset rstout wkpcfg pllcfg 3 4 bootcfg rstcfg MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 28 figure 6. jtag test clock input timing figure 7. jtag test access port timing tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 29 figure 8. jtag jcomp timing tck jcomp 9 10 MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 30 figure 9. jtag boundary scan timing tck output signals input signals output signals 11 12 13 14 15 electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 31 3.13.3 nexus timing figure 10. nexus output timing table 21. nexus debug port timing 1 1 jtag specifications apply when used for debug functionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dd = 1.35?1.65 v, v dde = 2.25?3.6 v, v dd33 and v ddsyn = 3.0?3.6 v, t a = t l to t h , and cl = 30 pf with dsc = 0b10. spec characteristic symbol min. max. unit 1 mcko cycle time t mcyc 1 2 2 the nexus aux port runs up to 82 mhz. set npc_pcr[mcko _div] to divide-by-two if the system frequency is greater than 82 mhz. 8t cyc 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo data valid 3 3 mdo, mseo , and evto data is held valid until the next mcko low cycle occurs. t mdov ?1.5 3.0 ns 4 mcko low to mseo data valid 3 t mseov ?1.5 3.0 ns 5 mcko low to evto data valid 3 t evtov ?1.5 3.0 ns 6 evti pulse width t evtipw 4.0 ? t tcyc 7 evto pulse width t evtopw 1?t mcyc 8 tck cycle time t tcyc 4 4 4 limit the maximum frequency to approximately 16 mhz (v dde = 2.25?3.0 v) or 20 mhz (v dde = 3.0?3.6 v) to meet the timing specification for t jov of [0.2 x t jcyc ] as outlined in the ieee-isto 5001-200 3 specification. ?t cyc 9 tck duty cycle t tdc 40 60 % 10 tdi, tms data setup time t ntdis, t ntmss 8?ns 11 tdi, tms data hold time t ntdih, t ntmsh 5?ns 12 tck low to tdo data valid t jov v dde = 2.25?3.0 v 0 12 ns v dde = 3.0?3.6 v 0 10 ns 13 rdy valid to mcko 5 5 the rdy pin timing is asynchronous to mcko and is guaranteed by design to function correctly. ???? 1 2 3 4 5 mcko mdo mseo evto output data valid MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 32 figure 11. nexus tdi, tms, tdo timing tdo 10 11 tms, tdi 12 tck electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 33 3.13.4 external bus interface (ebi) timing table 22 lists the timing information for the external bus interface (ebi). table 22. bus operation timing 1 spec characteristic and description symbol external bus frequency 2, 3 unit notes 40 mhz 56 mhz 66 mhz min. max. min. max. min. max. 1 clkout period t c 24.4 ? 17.5 ? 14.9 ? ns signals are measured at 50% v dde . 2 clkout duty cycle t cdc 45% 55% 45% 55% 45% 55% t c 3 clkout rise time t crt ?? 4 ?? 4 ?? 4 ns 4 clkout fall time t cft ?? 4 ?? 4 ?? 4 ns 5 clkout positive edge to output signal invalid or hi-z (hold time) external bus interface cs [0:3] addr[8:31] data[0:31] 5 bdip oe rd_wr ta tea 6 ts we /be [0:3] 7 t coh 1.0 8 1.5 ? 1.0 8 1.5 ? 1.0 8 1.5 ?ns ebts = 0 ebts = 1 hold time selectable via siu_eccr [ebts] bit. clkout positive edge to output signal invalid or hi-z (hold time) calibration bus interface cal_cs [0, 2:3] cal_addr[10:30] cal_data[0:15] cal_oe cal_rd_wr cal_ts cal_we /be [0:1] t ccoh 1.0 8 1.5 ? 1.0 8 1.5 ? 1.0 8 1.5 ?ns ebts = 0 ebts = 1 hold time selectable via siu_eccr [ebts] bit. MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 34 6 clkout positive edge to output signal valid (output delay) external bus interface cs [0:3] addr[8:31] data[0:31] 5 bdip oe rd_wr ta tea 6 ts we /be [0:3] 7 t cov ? 10.0 8 ? 11.0 ? 7.5 8 8.5 ? 6.0 8 7.0 ns ebts = 0 ebts = 1 output valid time selectable via siu_eccr [ebts] bit. 6a clkout positive edge to output signal valid (output delay) calibration bus interface cal_cs [0, 2:3] cal_addr[10:30] cal_data[0:15] cal_oe cal_rd_wr cal_ts cal_we /be [0:1] t ccov ? 11.0 8 ? 12.0 ? 8.5 8 9.5 ? 7.0 8 8.0 ns ebts = 0 ebts = 1 output valid time selectable via siu_eccr [ebts] bit. 7 input signal valid to clkout positive edge (setup time) external bus interface addr[8:31] data[0:31] 5 rd_wr ta tea 6 ts t cis 10.0 ? 7.0 ? 5.0 ? ns input signal valid to clkout positive edge (setup time) calibration bus interface cal_addr[10:30] cal_data[0:15] cal_rd_wr cal_ts t ccis 11.0 ? 8.0 ? 6.0 ? ns table 22. bus operation timing 1 (continued) spec characteristic and description symbol external bus frequency 2, 3 unit notes 40 mhz 56 mhz 66 mhz min. max. min. max. min. max. electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 35 figure 12. clkout timing 8 clkout positive edge to input signal invalid (hold time) external bus interface addr[8:31] data[0:31] 5 rd_wr ta tea 6 ts t cih 1.0 ? 1.0 ? 1.0 ? ns clkout positive edge to input signal invalid (hold time) calibration bus interface cal_addr[10:30] cal_data[0:15] cal_rd_wr cal_ts t ccih 1.0 ? 1.0 ? 1.0 ? ns 1 ebi timing specified at: v dde = 1.6?3.6 v (unless stated otherwise); t a = t l to t h ; and cl = 30 pf with dsc = 0b10. 2 speed is the nominal maximum frequency. max. speed is t he maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system cl ock + 2% fm; 114 mhz parts allow fo r 112 mhz system clock + 2% fm; and 135 mhz parts allow for 132 mhz system clock + 2% fm. 3 the external bus is limited to half the speed of the internal bus. 4 refer to fast pad timing in ta bl e 1 7 and ta bl e 1 8 (different values for 1.8 v and 3.3 v). 5 due to pin limitations, the data[16:31] signals are not available on the 324 package. 6 due to pin limitations, the tea signal is not available on the 324 package. 7 due to pin limitations, the we /be [2:3] signals are not available on the 324 package. 8 siu_eccr[ebts] = 0 timings are tested and valid at v dde = 2.25?3.6 v only; siu_eccr[ebts] = 1 timings are tested and valid at v dde = 1.6?3.6 v. table 22. bus operation timing 1 (continued) spec characteristic and description symbol external bus frequency 2, 3 unit notes 40 mhz 56 mhz 66 mhz min. max. min. max. min. max. 1 2 2 3 4 clkout v dde ?? 2 vol_f voh_f MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 36 figure 13. synchronous output timing 6 5 5 clkout bus 5 output signal output v dde ?? 2 v dde ?? 2 v dde ?? 2 v dde ?? 2 6 5 output signal v dde ?? 2 6 electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 37 figure 14. synchronous input timing 3.13.5 external interrupt timing (irq signals) table 23. external interrupt timing 1 1 irq timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . spec characteristic symbol min. max. unit 1 irq pulse-width low t ipwl 3?t cyc 2 irq pulse-width high t ipwh 3?t cyc 3 irq edge-to-edge time 2 2 applies when irq signals are configured for ri sing-edge or falling-edge events, but not both. t icyc 6?t cyc 7 8 clkout input bus 7 8 input signal v dde ?? 2 v dde ?? 2 v dde ?? 2 MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 38 figure 15. external interrupt timing 3.13.6 etpu timing figure 16. etpu timing table 24. etpu timing 1 1 etpu timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . spec characteristic symbol min. max unit 1 etpu input channel pulse width t icpw 4?t cyc 2 etpu output channel pulse width t ocpw 2 2 2 this specification does not include the rise and fall times. wh en calculating the minimum etpu pulse width, include the rise and fall times defined in the slew rate control fiel ds (src) of the pad configuration registers (pcr). ?t cyc irq 1 2 3 1 2 etpu output etpu input and tcrclk electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 39 3.13.7 emios timing figure 17. emios timing 3.13.8 dspi timing table 25. emios timing 1 1 emios timing specified at: v ddeh = 3.0?5.25 v and t a = t l to t h . spec characteristic symbol min. max. unit 1 emios input pulse width t mipw 4?t cyc 2 emios output pulse width t mopw 1 2 2 this specification does not include the rise and fall times. when calculating the minimum emios pulse width, include the rise and fall times defined in the slew rate control fi eld (src) in the pad conf iguration register (pcr). ?t cyc table 26. dspi timing 1 ? 2 spec characteristic symbol 80 mhz 112 mhz 132 mhz unit min. max. min. max. min. max. 1 sck cycle time 3, 4 t sck 24.4 ns 2.9 ms 17.5 ns 2.1 ms 14.8 ns 1.8 ms ? 2 pcs to sck delay 5 t csc 23 ? 15 ? 13 ? ns 3 after sck delay 6 t asc 22 ? 14 ? 12 ? ns 4 sck duty cycle t sdc (t sck ? 2) ? 2 ns (t sck ? 2) + 2 ns (t sck ? 2) ? 2 ns (t sck ? 2) + 2 ns (t sck ? 2) ? 2 ns (t sck ? 2) + 2 ns ns 5 slave access time (ss active to sout driven) t a ? 25 ? 25 ? 25 ns 6 slave sout disable time (ss inactive to sout hi-z, or invalid) t dis ? 25 ? 25 ? 25 ns 7pcs x to pcss time t pcsc 4?4?4?ns 8pcss to pcs x time t pasc 5?5?5?ns 1 2 emios output emios input MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 40 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 7 master (mtfe = 1, cpha = 1) t sui 20 2 ?4 20 ? ? ? ? 20 2 3 20 ? ? ? ? 20 2 6 20 ? ? ? ? ns ns ns ns 10 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 7 master (mtfe = 1, cpha = 1) t hi ?4 7 21 ?4 ? ? ? ? ?4 7 14 ?4 ? ? ? ? ?4 7 12 ?4 ? ? ? ? ns ns ns ns 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t suo ? ? ? ? 5 25 18 5 ? ? ? ? 5 25 14 5 ? ? ? ? 5 25 13 5 ns ns ns ns 12 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho ?5 5.5 8 ?5 ? ? ? ? ?5 5.5 4 ?5 ? ? ? ? ?5 5.5 3 ?5 ? ? ? ? ns ns ns ns 1 all dspi timing specifications use the fastest slew rate (s rc = 0b11) on pad type m or mh. dspi signals using pad types of s or sh have an additional delay based on the slew rate. dspi timing is specified at: v ddeh = 3.0?5.25 v;t a = t l to t h ; and cl = 50 pf with src = 0b11. 2 speed is the nominal maximum frequency. max. speed is th e maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system cl ock + 2% fm; 114 mhz parts allow fo r 112 mhz system clock + 2% fm; and 135 mhz parts allow for 132 mhz system clock + 2% fm. 3 the minimum sck cycle time restricts the baud rate selection for the given system clock rate. these numbers are calculated based on two mpc55xx devices communicating over a dspi link. 4 the actual minimum sck cycle time is limited by pad performance. 5 the maximum value is programmable in d spi_ctarx[pssck] and dspi_ctarx[cssck]. 6 the maximum value is programmable in dspi_ctarx[pasc] a nd dspi_ctarx[asc]. 7 this number is calculated using the smpl_pt field in dspi_mcr set to 0b10. table 26. dspi timing 1 ? 2 (continued) spec characteristic symbol 80 mhz 112 mhz 132 mhz unit min. max. min. max. min. max. electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 41 figure 18. dspi classic spi timing?master, cpha = 0 figure 19. dspi classic spi timing?master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 42 figure 20. dspi classic spi timing?slave, cpha = 0 figure 21. dspi classic spi timing?slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 43 figure 22. dspi modified transfer format timing?master, cpha = 0 figure 23. dspi modified transfer format timing?master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) MPC5565 microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 44 figure 24. dspi modified transfer format timing?slave, cpha = 0 figure 25. dspi modified transfer format timing?slave, cpha = 1 figure 26. dspi pcs strobe (pcss ) timing last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) pcsx 7 8 pcss electrical characteristics MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 45 3.13.9 eqadc ssi timing figure 27. eqadc ssi timing table 27. eqadc ssi ti ming charact eristics spec rating symbol minimum typical maximum unit 2 fck period (t fck = 1 ? f fck ) 1, 2 1 ss timing specified at v ddeh = 3.0?5.25 v, t a = t l to t h , and cl = 25 pf with src = 0b11. maximum operating frequency varies depending on track delays, master pad delays, and slave pad delays. 2 fck duty cycle is not 50% when it is generated through the division of the system clock by an odd number. t fck 2? 17t sys_clk 3 clock (fck) high time t fckht t sys_clk ? 6.5 ? 9 ? (t sys_clk ? 6.5) ns 4 clock (fck) low time t fcklt t sys_clk ? 6.5 ? 8 ? (t sys_clk ? 6.5) ns 5 sds lead / lag time t sds_ll ?7.5 ? +7.5 ns 6 sdo lead / lag time t sdo_ll ?7.5 ? +7.5 ns 7 eqadc data setup time (inputs) t eq_su 22 ? ? ns 8 eqadc data hold time (inputs) t eq_ho 1? ? ns 1st (msb) 2nd 25th 26th 1st (msb) 2nd 25th 26th 8 7 5 6 4 5 4 2 3 fck sds sdo external device data sample at sdi eqadc data sample at fck falling-edge fck rising-edge MPC5565 microcontroller data sheet, rev. 3 mechanicals freescale semiconductor 46 4 mechanicals 4.1 MPC5565 324 pbga pinouts figure 28 is a pinout for the mpc555346567 324 pbga package. note the mpc5500 devices are pin compatible for software portability and use the primary function names to label the pins in th e bga diagram. although some devices do not support all the pr imary functions shown in the bga diagram, the muxed and gpio signals on those pins remain available. see the signals chapter in the device reference manual for the signal muxing. figure 28. MPC5565 324 package vss 1 2 3 4 5 6 7 8 9 10111213141516171819202122 an28 vdd vstby an37 an11 vdda1 an1 an5 vrh vrl an27 an35 vssa0 mdo10 mdo8 vdd vdd33 vss a vdd33 an31 vss vdd an36 an39 an19 an0 an23 an26 an32 vssa0 mdo9 mdo7 mdo4 mdo0 vss vdde7 b an30 vss vdd an8 an17 an21 an3 an7 an22 an25 an33 vdda0 an14 mdo5 mdo2 mdo1 vss vdde7 vdd c an29 vss vdd an38 an10 an18 an2 an6 an24 an15 mdo6 vss vdde7 tck tdi d vdde7 tms tdo test e vdde7 jcomp evti evto f rdy g vss vss vss vss vss vdde7 vss vss vss vss vss vss vss vss vss vss vss vss sinb h vss vdde2 vdde2 vss vss vss soutb pcsb3 pcsb0 pcsb1 j vss vss vss vdde2 vss vss pcsa3 pcsb4 sckb pcsb2 k vss vss vss vdde2 vss vss pcsb5 souta sina scka l bdip cs1 cs0 pcsa1 pcsa0 pcsa2 vpp m cs2 we1 we0 pcsa4 txda pcsa5 vflash n rd_wr cntxc rxda rstout p rxdb cnrxc txdb reset r ts t extal u vdde2 vdd xtal v vss vdd vdde2 vdde5 nc vss vdd vrc33 w vss vdd cntxa vdde5 nc vss vdd vdd33 y vss vdd cnrxa vdde5 clkout vss vdd aa vss vdd vdde2 vdde2 cntxb cnrxb vdde5 vss ab a b c d e f g h j k l m n p r t u v 1 2 3 4 5 6 7 8 9 10111213141516171819202122 an9 an20 an16 vssa1 etpua 28 etpua 29 etpua 25 etpua 24 etpua 27 etpua 23 etpua 22 etpua 17 etpua 20 etpua 19 etpua 14 etpua 13 etpua 16 etpua 15 etpua 10 vddeh 1 etpua 6 gpio 204 gpio 203 vddeh 10 addr 16 addr 17 addr 18 addr 19 addr 20 addr 21 addr 12 addr 22 addr 23 addr 13 addr 25 addr 31 addr 15 addr 26 addr 24 addr 30 addr 28 addr 27 addr 29 data 0 data 1 data 8 data 3 data 9 data 4 data 13 gpio 206 data 5 data 10 data 11 data 12 data 14 data 15 data 7 emios 6 emios 2 emios 10 emios 15 vddeh 4 emios 12 emios 17 emios 16 emios 14 emios 22 emios 19 emios 18 emios 23 emios 20 emios 21 boot cfg1 vddeh 6 pll cfg1 boot cfg0 wkp cfg vss syn vrc ctl pll cfg0 vdd syn rst cfg eng clk note: no connect. reserved (w18 & y19 are shorted to each other) nc w y aa ab mdo11 an12 an4 ref bypc an13 etpua 30 etpua 31 etpua 26 etpua 21 etpua 18 an34 vddeh 9 mdo3 etpua 11 etpua 12 etpua 2 etpua 7 etpua 8 etpua 0 tcrclk a etpua 3 etpua 4 etpua 9 etpua 5 etpua 1 mcko mseo0 mseo1 cs3 vdd33 ta vdde2 addr 14 vdde2 vdd33 emios 8 vdde2 vdde2 vdde2 gpio 207 data 2 data 6 emios 13 emios 9 emios 5 emios 3 oe emios 11 emios 7 emios 4 emios 1 emios 0 pll cfg2 mechanicals MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 47 4.2 MPC5565 324-pin package dimensions the package drawings of the MPC5565 324-pin tepbga package are shown in figure 29 . figure 29. MPC5565 324 tepbga package MPC5565 microcontroller data sheet, rev. 3 mechanicals freescale semiconductor 48 figure 29. MPC5565 324 tepbga package (continued) revision history for the MPC5565 data sheet MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 49 5 revision history for the MPC5565 data sheet the history of revisions made to th is data sheet are shown in this s ection. the changes are divided into each revision of this document. the substantive cha nges incorporated in mpc 5565 data sheet rev. 1.0 to produce rev. 2.0 of this doc ument are grouped as follows: ? global and text changes ? table and figure changes within each group, the changes ar e listed in sequential order. 5.1 changes between revisi on 2.0 and revision 3.0 5.2 changes between revisi on 1.0 and revision 2.0 the following table lists the substantiv e text changes made to paragraphs. section 3.7, ?power-up/down sequencing ? added the following paragraph in section 3.7, ?power-up/down sequencing ?: ?during initial power ramp-up, when vstby is 0.6v or above. a typical current of 1-3ma and maximum of 4ma may be seen until vdd is applied. this current will not reoccur until vstby is lowered below vstby min. specification?. moved figure 2 (fistby worst-case specifications) ?istby worst-case specifications? to section 3.7, ?power-up/down sequencing ?. section 3.8, ?dc electrical specifications ? removed the footnote ?figure 3 shows an illustration of the idd_stby values interpolated for these temperature values?. changed the footnote attached to idd_stby to ?the current specification relates to average standby operation after sram has been load ed with data. for power up current see section 3.7, ?power-up/down sequencing ?, figure 2 (fistby worst-case specifications) .? in table 9 (dc electrical specifications (t a = t l to t h )) the characteristic ?refer to figure 3 for an interpolation of this data? changed to ?ram standby current?. table 28. text changes between rev. 1.0 and 2.0 location description of changes throughout: changed ?t a = t l ? t h ? to ?t a = t l to t h .? title page: changed the revision number from 1.0 to 2.0. made the sa me changes in the lower left corner of the back page. section 1, ?overview? ? fourth paragraph, first sentence: deleted ?of the mpc5 500 family?; second to last sentence: deleted ?can?. ? fifth paragraph, first sentence: replaced ?mpc5500 fa mily? with ?MPC5565?; last sentence: replaced ?can be? with ?is?. ? sixth paragraph, first sentence: replaced ?mpc5500 family? with ?MPC5565?; ? second to last paragraph: rewrote to read: the mcu has an on-chip enhanced queued dual analog-to-digital converter (eqadc) the 324 package has 40-channels. MPC5565 microcontroller data sheet, rev. 3 revision history for the MPC5565 data sheet freescale semiconductor 50 the following table lists the information that changed in the tables between rev. 1.0 and 2.0. section 3.1, ?maximum ratings: changed title from ?maximum rating? to ?maximum ratings.? section 3.2.1, ?general notes for specifications at maximum junction temperature ? updated the address of semiconductor equipment and materials international 3081 zanker rd. san jose, ca., 95134 (408) 943-6900 section 3.7, ?power-up/down sequencing ? last paragraph: changed the first sentence from , , , t he voltage on the pins goes to high-impedance until . . . to. . .the pins go to a high-impedance state until . . . section 3.7.3, ?power-down sequence (vrc33 grounded) ? last sentence: changed from: ?t his ensures that the digital 1.5 v logic, which is reset by the ored por only and can cause the 1.5 v supply to decrease belo w its specification, is reset properly.? to: ?this ensures that the digital 1.5 v logic, which is reset only by an ored por and can cause the 1.5 v supply to decrease less than its specif ication, resets correctly.? section 4.1, ?MPC5565 324 pbga pinouts? added the following note before the 324 bga map: note the mpc5500 devices are pin compatible fo r software portability and use the primary function names to label the pins in the bga diagram. although some devices do not support all the primary functions shown in the bga diagram, the muxed and gpio signals on those pins remain available. see the signals chapter in the device reference manual for the signal muxing. table 29. MPC5565 changes between rev. 1.0 and 2.0 location description of changes table 2 (absolute maximum ratings) absolute maximum ratings: ? added footnote 7 to spec 12 ?internal structures hold the input voltage le ss than the maximum voltage on all pads powered by v dde supplies, if the maximum injection current sp ecification is met (2 ma for all pins) and v dde is within the operating voltage specifications.? table 4 (emi testing specifications) emi testing specifications: ? table title: footnote 1: deleted the last sentence: ?the values in this sp ecification reflect emi performance with frequency modulation (fm) turned off. for better emi performance, enable fm.? table 5 (esd ratings ,) esd ratings: changed footnote 2 from: ? ?device failure is defined as: ?if after exposure to esd pulses, the device no longer m eets the device specification requirements. complete dc parametric and functional testing will be performed per applicable device specification at room temperature followed by hot te mperature, unless specified otherwise in the device specification.? to: ? device failure is defined as: ?if after exposure to esd pulses, the device does not meet the device specification requirements, which includes the complete dc parametric and functional testing at room temperature and hot temperature. table 28. text changes between rev. 1.0 and 2.0 (continued) location description of changes revision history for the MPC5565 data sheet MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 51 ta bl e 6 ( v rc and por electrical specifications) vcr/por electrical specifications: ? added footnote 1 to specs 1, 2, and 3 that reads: the internal por signals are v por15 , v por33 , and v por5 . on power up, assert reset before the intern al por negates. reset must remain asserted until the power supplies are within the operating conditions as specified in table 9 (dc electrical specifications (t a = t l to t h )) dc electrical specifications. on power down, assert reset before any power supplies fall outside the operating conditions and until the internal por asserts. ? reformatted columns. table 9 (dc electrical specifications (t a = t l to t h )) dc electrical specifications: ? added (t a = t l to t h ) to the table title. ? added footnote that reads: v dde2 and v dde3 are limited to 2.25?3.6 v on ly if siu_eccr[ebts] = 0; v dde2 and v dde3 have a range of 1.6?3.6 v if siu_eccr[ebts] =1. table 17 (pad ac specifications (vddeh = 5.0 v, vdde = 1.8 v)) pad ac specifications: ? footnote 1, changed ?v ddeh = 4.5?5.5;? to ?v ddeh = 4.5?5.25;? ? footnote 3, changed from ?out delay. . .? to ?the output delay. . .?, ? changed from ? add a maximum of one system clock to th e output delay to get the out put delay with respect to the system clock?to ?to calculate the ou tput delay with re spect to the system clock, add a maximum of one system clock to the output delay.? ? footnote 4: changed ?delay? to ?the output delay.? table 19 (reset and configuration pin timing) reset and configuration pin timing ? footnote 1: removed v dd =1.35?1.65. table 20 (jtag pin ac electrical characteristics) jtag pin ac electrical characteristics ? footnote 1: removed v dd =1.35?1.65; and v dd33 and v ddsyn = 3.0?3.6 v. table 22 (bus operation timing) bus operation timing: ? specifications 5 and 6. changed ebts to siu_eccr[ebts]. ? specifications 7 and 8: removed cs [0:3], bdip , oe , and we /be [0:3] because these pins are not used on the input signal to clkout. ? specification 7: removed cal_cs [0, 2:3], cal_oe , and cal_we /be [0:1] because these pins are not used on the input signal to clkout. ? specification 8: added to the beginning of the calibrat ion section: clkout positive edge to input signal invalid (hold time). removed cal_cs [0, 2:3], cal_oe , and cal_we /be [0:1] because these pins are not used on the input signal to clkout. ? footnote 1: deleted v dd = 1.35?1.65; and v dd33 and v ddsyn = 3.0?3.6 v. ? added footnote 2: ?speed is the nominal maximum frequency. max. speed is the maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm; and 135 mh z parts allow for 132 mhz system clock + 2% fm.? ? added footnotes 5, 6, and 7, one each for the data[0:31], tea , and we /be [0:3] signals in the table: due to pin limitations, the da ta[16:31], tea , and we /be [2:3] signals are not available on the 324 package. ? footnote 8: changed ebts to siu_eccr[ebts]. table 23 (external interrupt timing) external interrupt timing (irq signals) ? footnote 1: removed v dd = 1.35?1.65 v; changed v ddeh = 3.0?5.5 v to v ddeh = 3.0?5.25 v. table 24 (etpu timing) etpu timing ? footnote 1: changed v ddeh = 3.0?5.5 v to v ddeh = 3.0?5.25 v. table 25 (emios timing) emios timing ? footnote 1: changed v ddeh = 3.0?5.5 v to v ddeh = 3.0?5.25 v. table 26 (dspi timing?) dspi timing: table 29. MPC5565 changes between rev. 1.0 and 2.0 (continued) location description of changes MPC5565 microcontroller data sheet, rev. 3 revision history for the MPC5565 data sheet freescale semiconductor 52 5.3 changes between revisi on 0.0 and revision 1.0 the following table lists the information that changed in the tables between rev. 0.0 and 1.0. ? specification 1: sck cycle time. cha nged 80 mhz column, min.: from 25 to 24.4; 112 mhz columns, min.: from 17.9 to 17.5, max: from 2.0 to 2.1; 132 mhz column s, min.: from 15.2 to 14.8, max: from 1.7 to 1.8. ? footnote 1, changed ?v ddeh = 3.0?5.5 v;? to ?v ddeh = 3.0?5.25 v;? ? table title: added footnote that reads: speed is the nominal maximum frequency. max speed is the maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm, 135 mhz parts allow for 1 32 mhz system clock + 2% fm. table 27 (eqadc ssi timing characteristics) eqadc ssi timing characteristics ? footnote 1: changed v ddeh = 3.0?5.5 v to v ddeh = 3.0?5.25 v. table 30. MPC5565 changes between rev. 0.0 and 1.0 location description of changes ta bl e 6 ( v rc and por electrical specifications) vcr/por electrical specifications: ? added footnote 1 to specs 1, 2, and 3 that read s: on power up, assert reset before v por15 , v por33 , and v por5 negate (internal por) . reset must remain asserted until the power supplies are wit hin the operating conditions as specified in table 9 (dc electrical specifications (t a = t l to t h )) dc electrical specifications. on power down, assert reset before any power supplies fall outside the operating conditions and until the internal por asserts. table 9 (dc electrical specifications (t a = t l to t h )) dc electrical specifications: ? added (t a = t l to t h ) to the table title. table 22 (bus operation timing) bus operation timing: ? external bus frequency in the table heading: adde d footnote that reads: speed is the nominal maximum frequency. max speed is the maximum speed allowed including frequency modulation (fm). 82 mhz parts allow for 80 mhz system clock + 2% fm; 114 mhz parts allow for 112 mhz system clock + 2% fm, and 135 mhz parts allow for 132 mhz system clock + 2% fm. ? specifications 5, 6, 7, and 8: reorder ed the ebi signals within each specification. ? specs 7 and 8: removed from external bus interface: bdip , oe , and we /be [0:3]. ? footnote 1: removed v dd = 1.35?1.65 v, and v dd33 and v ddsyn = 3.0?3.6 v. table 25 (emios timing) emios timing: ? deleted (mts) from the heading, table, and footnotes. ? footnote 1: deleted ?. . .f sys = 132 mhz. . .?, ?. . .v dd33 and v ddsyn = 3.0?3.6 v. . .? and ? . . .and cl = 200 pf with src = 0b11.? ? added footnote 2: ?this specificatio n does not include the rise and fall times. when calculating the minimum emios pulse width, include the rise and fall times defined in the slew rate control fields (src) of the pad configuration registers (pcr).? table 29. MPC5565 changes between rev. 1.0 and 2.0 (continued) location description of changes MPC5565 microcontroller data sheet, rev. 3 freescale semiconductor 53 this page is intentionally blank document number: mpc55565 rev. 3 5/2012 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2008,2012. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . |
Price & Availability of MPC5565
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |